1. Field of the Invention
The invention relates to an arrangement for predictive encoding in which an encoder encodes the difference which exist between the codewords supplied by a source and the codewords obtained from the output of the encoder after being converted by a decoder and delayed by a memory over a number of word periods, and in which the write-read operation of the memory is controlled by a cyclic address counter which is controlled by pulses occurring at word rate.
Such arrangements are required, for example, in video conference systems; they play a significant role in bit rate reduction.
2. Description of the Prior Art
An arrangement of the type mentioned above is described, for example, in published European Patent Application No. 0,103,380. According to this Application the PCM codewords originating from a video camera are applied to a DPCM encoder at word rate, which codewords contain information on luminance and chrominance of the picture elements. Together with each codeword from the video camera a codeword from a picture memory is applied to the DPCM encoder, which codeword is associated with the same picture element but is delayed over one full picture period. The PCM codewords written into the picture memory are produced by reconverting the DPCM codewords using a DPCM decoder. The known arrangement is an encoding arrangement with a so-called feedback prediction.
Writing and reading of the codewords from the picture memory can be controlled with a single address counter which is controlled by control pulses occurring at word rate. The address counter cyclically generates all addresses of the memory locations of the picture memory, each such location storing a codeword associated with a given picture element. When the address counter generates an address, the codeword stored in the relevant memory location is read and subsequently a new codeword associated with the same picture element is stored. Reading and writing of the codewords associated with a given picture element are temporally offset over one full picture period, but has to take place within 400 ns, for example, in a video conference system. This means, inter alia, that the encoder and the decoder must generate the new codeword within 400 ns. If the encoder and decoder are not so fast, for example, if they require 3 word periods to generate the new codeword, it is impossible in a simple RAM to always use the same memory location for a picture element. If this situation is encountered, two counters and one picture memory must be used such that these counters seperately control the write and read processes. Such a memory is used, for example, in circuit arrangements for converting motion picture signals, as proposed in published European Patent Application No. 0,089 919. If in the relevant case--in which there is a delay of 3 word periods between the instant at which a codeword is read from the memory and a new codeword for the same picture element is generated--such a picture memory is used, the two counters should both cyclically generate the N addresses of the picture memory, phase shifted over three word periods, with the leading counter controlling the reading process and the trailing counter controlling the writing process and N being the number of codewords to be stored and associated with a full picture. It is also feasible to delay the addresses of a counter by three word periods and to subsequently control the writing process with the delayed addresses; in each case an extremely fast RAM and high-frequency pulses would be required for the control.